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october 2012 doc id 15912 rev 2 1/22 AN3002 application note description of the m24lrxx-r and m24lrxxe-r dual interface memory?s password protection mechanism description the m24lrxx-r or m24lrxxe-r device is a dual-interface, electrically erasable programmable memory (eepr om). it features an i 2 c interface and can be operated from a v cc power supply. it is also a contactless memory powered by the received electromagnetic carrier wave. the m24lrxx-r or m24lrxxe-r is organized as 8192 8 bits in the i 2 c mode and as 2048 32 bits in the iso 15693 and iso 18000-3 mode 1 rf mode. figure 1. m24lrxx block diagram ta bl e 1 lists the products concerned by this application note. note: the standard m24lrxx-r and energy-harvesting m24lrxxe-r devices will be referred to as m24lrxx devices throughout the document. table 1. applicable products type applicable products dual interface eeproms m24lrxx-r, m24lrxxe-r eeprom row decoder latch logic rf i 2 c rf v cc contact v cc scl sda v ss v cc ac0 ac1 power management ai15123 www.st.com
contents AN3002 2/22 doc id 15912 rev 2 contents 1 user memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2i 2 c password mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 m24lrxx i2c password security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1.1 i 2 c present password command description . . . . . . . . . . . . . . . . . . . . . 7 2.1.2 i2c write password command description . . . . . . . . . . . . . . . . . . . . . . . 8 3 rf password mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4 m24lrxx?s conditional memory access . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1 m24lrxx?s conditional memory access using passwords . . . . . . . . . . . . 13 4.1.1 i 2 c access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 4.1.2 rf access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4.1.3 mixed rf and i 2 c access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
AN3002 list of tables doc id 15912 rev 2 3/22 list of tables table 1. applicable products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. i2c_write_lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 table 3. sector security status byte area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. sector security status byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 table 5. read / write protection bit setting. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 6. password control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 7. password system area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 8. i2c_write_lock bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 table 9. i 2 c memory access condition at power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 10. i 2 c memory access cond ition after a valid i 2 c present password . . . . . . . . . . . . . . . . . . . 15 table 11. i2c_write_lock bit update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 12. i 2 c memory access condition at next power on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 13. rf memory access conditions at power-on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 14. rf memory access condition after a valid present-sector password. . . . . . . . . . . . . . . . . 17 table 15. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
list of figures AN3002 4/22 doc id 15912 rev 2 list of figures figure 1. m24lrxx block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. memory sector organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 figure 3. i 2 c present password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. i 2 c write password command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 5. m24lrxx memory sharing concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. rf multiple password memory access condition at power-up . . . . . . . . . . . . . . . . . . . . . . 18 figure 7. rf multiple password memory access condition after password 1 presentation . . . . . . . . 18 figure 8. rf multiple password memory access condition after password 2 presentation . . . . . . . . 19 figure 9. m24lrxx rf and i 2 c access condition mix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. example of an rf capab ility extension in an ap plication running with an eeprom . . . . . 20
AN3002 user memory organization doc id 15912 rev 2 5/22 1 user memory organization the m24lrxx is divided into 64 sectors of 32 blocks of 32 bits. figure 2 shows the memory sector organization. each sector can be individually read- and/or write-protected using a specific password command. read and write operations are possible if the addressed data is not in a protected sector. the m24lrxx also has a 64-bit block that is used to store the 64-bit unique identifier (uid). the uid is compliant with the iso 15963 description, and its value is used during the anticollision sequence (inventory). this block is not accessible by the user and its value is written by st on the production line. the m24lrxx includes an afi register that stores the application family identifier, and a dsfid register that st ores the data storage family iden tifier used in the anticollision algorithm. the m24lrxx has four additional 32-bit blocks that store an i 2 c password plus three rf password codes. figure 2. memory sector organization sector details the m24lrxx user memory is divided into 64 sectors. each sector contains 1024 bits. in rf mode, a sector provides 32 blocks of 32 bits. each read / write access is done by block. read and write block accesses are controlled by a sector security status byte that defines the access rights to all the 32 blocks contained in the sector. if the sector is not protected, a write command updates all 32 bits of the selected block. 0 1 kbit eeprom sector 5 bits 1 1 kbit eeprom sector 5 bits 2 1 kbit eeprom sector 5 bits 3 1 kbit eeprom sector 5 bits 60 1 kbit eeprom sector 5 bits 61 1 kbit eeprom sector 5 bits 62 1 kbit eeprom sector 5 bits 63 1 kbit eeprom sector 5 bits i2c password system rf password 1 system rf password 2 system rf password 3 system 8 bit dsfid system 8 bit afi system 64 bit uid system sector area sector security status ai15124
user memory organization AN3002 6/22 doc id 15912 rev 2 in i 2 c mode, a sector provides 128 bytes that can be individually accessed in read and write modes. when protected by the corresponding i2c_write_lock bit, the entire sector is write- protected. to access the user memory, the device select code used for any i 2 c command must have the e2 chip enable address at 0.
AN3002 i 2 c password mechanisms doc id 15912 rev 2 7/22 2 i 2 c password mechanisms in the i 2 c mode only, it is possible to protect individual sectors against write operations. this feature is controlled by the i2c_write_lock bits stored in the 8 bytes of the i2c_write_lock bit area starting from the location 2048 (see ta bl e 2 ). using these 64 bits, it is possible to write-protect all the 64 sectors in the m24lrxx memory. each bit controls the i 2 c write access to a specific sector as shown in ta b l e 2 . it is always possible to unprotect a sector in the i 2 c mode. when an i2c_write_lock bit is reset to 0, the corresponding sector is unprotected. when the bit is set to 1, the corresponding sector is write-protected. in i 2 c mode, read access to the i2c_write_lock bit area is always allowed. write access depends on the correct presentation of the i 2 c password. to access the i2c_write_lock bit area, the device select code used for any i 2 c command must have the e2 chip enable address at 1. on delivery, the default value of the 8 bytes of the i2c_write_lock bit area is reset to 00h. 2.1 m24lrxx i2c password security the m24lrxx controls the i 2 c sector write access using the 32-bit-long i 2 c password and the 64-bit i2c_write_lock bit area. the i 2 c password value is managed using two i 2 c commands: i 2 c present password and i 2 c write password. 2.1.1 i 2 c present password command description the i 2 c present password command is used in the i 2 c mode to present the password to the m24lrxx in order to modify the write access rights of all the memory sectors protected by the i2c_write_lock bits, including the password itself. if the presented password is correct, the access rights remain activated until the m24lrxx is powered off or until a new i 2 c present password command is issued. following a start condition, the bus master sends a device select code with the read/write bit (rw ) reset to 0 and the chip enable bit e2 at 1. the device acknowledges this, as shown in figure 3 , and waits for two i 2 c password address bytes, 09h and 00h. the device responds to each address byte with an acknowledge bit, and then waits for the 4 password data bytes, the validation code, 09h, and a resend of the 4 password data bytes. the most significant byte of the password is sent first, followed by the least significant bytes. it is necessary to send the 32-bit password twice to prevent any data corruption during the sequence. if the two 32-bit passwords sent are not exactly the same, the m24lrxx does not start the internal comparison. table 2. i2c_write_lock bit i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] e2 = 1 2048 sectors 31-24 sectors 23-16 sectors 15-8 sectors 7-0 e2 = 1 2052 sectors 63-56 sectors 55-48 sectors 47-40 sectors 39-32
i 2 c password mechanisms AN3002 8/22 doc id 15912 rev 2 when the bus master generates a stop condition immediately after the ack bit (during the ?10 th bit? time slot), an internal delay equivalent to the write cycle time is triggered. a stop condition at any other time does not trigger the internal delay. during that delay, the m24lrxx compares the 32 received data bits with the 32 bits of the stored i 2 c password. if the values match, the write access rights to all protected sectors are modified after the internal delay. if the values do not match, the protected sectors remain protected. during the internal delay, serial data (sda) is disabled internally, and the device does not respond to any requests. figure 3. i 2 c present password command 2.1.2 i2c write password command description the i 2 c write password command is used to write a 32-bit block into the m24lrxx i 2 c password system area. this command is used in i 2 c mode to update the i 2 c password value. it cannot be used to update any of the rf passwords. after the write cycle, the new i 2 c password value is automatically activated. the i 2 c password value can only be modified after issuing a valid i 2 c present password command. on delivery, the i 2 c default password value is set to 0000 0000h and is activated. following a start condition, the bus master sends a device select code with the read/write bit (rw ) reset to 0 and the chip enable bit e2 at 1. the device acknowledges this, as shown in figure 4 , and waits for the two i 2 c password address bytes, 09h and 00h. the device responds to each address byte with an acknowledge bit, and then waits for the 4 password data bytes, the validation code, 07h, and a resend of the 4 password data bytes. the most significant byte of the password is sent first, followed by the least significant bytes. it is necessary to send twice the 32-bit password to prevent any data corruption during the write sequence. if the two 32-bit passwords sent are not exactly the same, the m24lrxx does not modify the i 2 c password value. when the bus master generates a stop condition immediately after the ack bit (during the 10 th bit time slot), the internal write cycle is triggered. a stop condition at any other time does not trigger the internal write cycle. during the internal write cycle, serial data (s da) is disabled internally, and the device does not respond to any requests. ai15125b start device select code password address 09h password address 00h password [31:24] ack r/w ack ack ack device select code = 1010 1 e1 e0 password [23:16] password [15:8] password [7:0] ack ack ack ack generated during 9 th bit time slot. stop validation code 09h ack password [31:24] ack password [23:16] password [15:8] password [7:0] ack ack ack
AN3002 i 2 c password mechanisms doc id 15912 rev 2 9/22 figure 4. i 2 c write password command ai15126 start device select code password address 09h password address 00h new password [31:24] ack r/w ack ack ack device select code = 1010 1 e1 e0 new password [23:16] new password [15:8] new password [7:0] ack ack ack ack generated during 9 th bit time slot. stop validation code 07h ack new password [31:24] ack new password [23:16] new password [15:8] new password [7:0] ack ack ack
rf password mechanisms AN3002 10/22 doc id 15912 rev 2 3 rf password mechanisms the m24lrxx provides a special protection mechanism based on passwords. each memory sector of the m24lrxx can be individually protected by one out of three available passwords, and each sector can also have read/write access conditions set. each memory sector in the m24lrxx is assigned with a sector security status byte including a sector lock bit, two password control bits and two read/write protection bits as shown in ta b l e 3 . ta bl e 4 describes the organization of the sector security status (sss) byte. this byte can be read using the read single block and read multiple block commands with the option_flag set to ?1?. on delivery, the default value of the sss bytes is reset to 00h. when the sector lock bit is set to ?1?, for instance by issuing a lock-sector password command, the 2 read/write protection bits (b1, b2) are used to set the read/write access of the sector as described in ta b l e 5 . table 3. sector security status byte area rf address i 2 c byte address bits [31:24] bits [23:16] bits [15:8] bits [7:0] 0 e2 = 1 0 sss 3 sss 2 sss 1 sss 0 128 e2 = 1 4 sss 7 sss 6 sss 5 sss 4 256 e2 = 1 8 sss 11 sss 10 sss 9 sss 8 384 e2 = 1 12 sss 15 sss 14 sss 13 sss 12 512 e2 = 1 16 sss 19 sss 18 sss 17 sss 16 640 e2 = 1 20 sss 23 sss 22 sss 21 sss 20 768 e2 = 1 24 sss 27 sss 26 sss 25 sss 24 896 e2 = 1 28 sss 31 sss 30 sss 29 sss 28 1024 e2 = 1 32 sss 35 sss 34 sss 33 sss 32 1152 e2 = 1 36 sss 39 sss 38 sss 37 sss 36 1280 e2 = 1 40 sss 43 sss 42 sss 41 sss 40 1408 e2 = 1 44 sss 47 sss 46 sss 45 sss 44 1536 e2 = 1 48 sss 51 sss 50 sss 49 sss 48 1664 e2 = 1 52 sss 55 sss 54 sss 53 sss 52 1792 e2 = 1 56 sss 59 sss 58 sss 57 sss 56 1920 e2 = 1 60 sss 63 sss 62 sss 61 sss 60 table 4. sector security status byte organization b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 0 0 0 password control bits read / write protection bits sector lock
AN3002 rf password mechanisms doc id 15912 rev 2 11/22 the next 2 bits of the sector security status byte (b 3 , b 4 ) are the password control bits. the value of these two bits is used to link a password to the sector as defined in ta b l e 6 . the m24lrxx password protection is organized around a dedicated set of commands plus a system area of three password blocks where the password values are stored. this system area is described in ta b l e 7 . the dedicated password commands are: write-sector password the write-sector password command is used to write a 32-bit block into the password system area. this command must be used to update password values. after the write cycle, the new password value is automatically activated. it is possible to modify a password value after issuing a valid present-sector password command. on delivery, the three default password values are set to 0000 0000h and are activated. lock-sector password the lock-sector password command is used to set the sector security status byte of the selected sector. bits b 4 to b 1 in the sector security status byte are affected by the lock- sector password command. the sector lock bit, b 0 , is set to ?1? automatically. after issuing a lock-sector password command, the protection settings of the selected sector are activated. the protection of a locked block cannot be changed in rf mode. table 5. read / write protection bit setting sector lock b 2 , b 1 sector access when password presented sector access when password not presented 0 xx read write read write 1 00 read write read no write 1 01 read write read write 1 10 read write no read no write 1 11 read no write no read no write table 6. password control bits b 4 , b 3 password 00 no password protection: password 0 condition 01 the sector is protected by the password 1 10 the sector is protected by the password 2 11 the sector is protected by the password 3 table 7. password system area add 0 7 8 15 16 23 24 31 1 password 1 2 password 2 3 password 3
rf password mechanisms AN3002 12/22 doc id 15912 rev 2 a lock-sector password command sent to a locked sector returns an error code. present-sector password the present-sector password command is used to present one of the three passwords to the m24lrxx in order to modify the access rights of all the memory sectors linked to that password ( ta b l e 5 ) including the password itself. if the presented password is correct, the access rights remain activated until the tag is powered off or until a new present-sector password command is issued. if the presented password value is not correct, all the access rights of all the memory sectors are deactivated. sector security status byte area access conditions in i 2 c mode in i 2 c mode, read access to the sector security status byte area is always allowed. write access depends on the correct presentation of the i 2 c password (see i2c present password command description ). to access the sector security status byte area, the device select code used for any i 2 c command must have the e2 chip enable address at 1. an i 2 c write access to a sector security status byte re-initializes the rf access condition to the given memory sector.
AN3002 m24lrxx?s conditional memory access doc id 15912 rev 2 13/22 4 m24lrxx?s conditional memory access the 64 sectors of the m24lrxx are shared between i 2 c and rf accesses. data written in rf mode can be read in i 2 c and data written in i 2 c can be read in rf, if the granted access authorizes it. this feature provides an easy way of sharing data between contact access using the i 2 c bus, on a pcb-based application for example, and rf access using an rfid reader/writer. figure 5. m24lrxx memory sharing concept 4.1 m24lrxx?s conditional memory access using passwords 4.1.1 i 2 c access in the following example, the initial setting of the m24lrxx is described in the ta bl e 8 and ta bl e 9 below. sectors 1 and 2 in the memory are protected against write accesses: bits b1 and b2 in the i2c_write lock bit area are set to 1. i2c a cce ss m24lrxx rf a cce ss memory d a t a a cce ss in re a d a nd write mode s 0x12 3 4567 8 01010 0x12 3 4567 8 01010 d a t a a cce ss in write mode 0x12 3 4567 8 0x12 3 4567 8 d a t a a cce ss in re a d mode 01010 01010 01010 01010 d a t a a cce ss in re a d mode d a t a a cce ss in write mode d a t a a cce ss in re a d a nd write mode s a i17125 table 8. i2c_write_lock bit i 2 c address bits[31:24] bits[23:16] bits[15:8] bits[7:0] 2048 0000 0000b 0000 0000b 0000 0000b 0000 0110b 2052 0000 0000b 0000 0000b 0000 0000b 0000 0000b
m24lrxx?s conditional memory access AN3002 14/22 doc id 15912 rev 2 m24lrxx memory access after i 2 c power-on after a correct i 2 c power-on condition, the m24lrxx offers the sector access conditions shown in table 9: i2c memory access condition at power on . all the memory sectors can be read, and write operations are allowed on all sectors except for sectors 1 & 2. note: the i2c_write lock bit area can be accessed in read mode only. m24lrxx memory access after a valid i 2 c present password command after a valid i 2 c present password command, assuming that the 32-bit password matched, the m24lrxx?s sector access conditio ns are modified as described in ta b l e 1 0 : i 2 c m e m o r y access condition after a valid i2c present password . all the 64 sectors of the m24lrxx are open to any write and read commands. the i2c_write lock bit area can also be updated to remove or add sector write protections. the write protection of the sector 2 can be removed by resetting bit b2 to 0 and the sectors 62 & 63 can be write-protected by setting the bits b62 & b63 to 1. note: it is also possible to update the sector security status bytes used to define the read and write rf accesses to the m24lrxx sectors. the i 2 c bus gives full control over the rf sector access conditions. this feature allows the main application system connected to the i 2 c bus to fully control the m24lrxx access conditions for both i 2 c and rf. table 9. i 2 c memory access condition at power on access condition m24lrxx user memory read and write sector 0 read only sector 1 read only sector 2 read and write sector 3 read and write ? read and write sector 62 read and write sector 63 read only i2c_write lock bit area read only sector_security_status area
AN3002 m24lrxx?s conditional memory access doc id 15912 rev 2 15/22 at the next m24lrxx power-on, the memory access conditions revert to the ones shown in table 11: i2c_write_lock bit update and table 12: i2c memory access condition at next power on . 4.1.2 rf access in rf, via the iso15693 or iso18000-3 mode 1 contactless protocol, the m24lrxx?s read and write sector access conditions are selected using the sector security status bytes. table 10. i 2 c memory access condition after a valid i 2 c present password access condition m24lrxx user memory read and write sector 0 read and write sector 1 read and write sector 2 read and write sector 3 read and write ? read and write sector 62 read and write sector 63 read and write i2c_write lock bit area read and write sector_security_status area table 11. i2c_write_lock bit update i 2 c address bits[31:24] bits[23:16] bits[15:8] bits[7:0] 2048 0000 0000b 0000 0000b 0000 0000b 0000 0010b 2052 1100 0000b 0000 0000b 0000 0000b 0000 0000b table 12. i 2 c memory access condition at next power on access condition m24lrxx user memory read and write sector 0 read only sector 1 read and write sector 2 read and write sector 3 read and write ? read only sector 62 read only sector 63 read only i2c_write lock bit area read only sector_security_status area
m24lrxx?s conditional memory access AN3002 16/22 doc id 15912 rev 2 through the setting of bits b1 & b2 (see table 5: read / write protection bit setting ), it is possible to: write-protect a sector, in which case the sector?s data is read-only read-protect a sector, in which case the sector?s data is not accessible from the rf in the following example, the initial setting of the m24lrxx is described in ta bl e 1 3 . sectors 0 to 3 are protected against various read and write access conditions as defined by the values of their sector security status bits, b1 and b2. m24lrxx memory access after rf power-on after a correct rf power-on condition, the m24lrxx offers the sector access conditions shown in table 13: rf memory access conditions at power-on . all the memory sectors can be read except for sectors 2 & 3, and write operations are allowed on all the sectors except for sectors 0, 2 & 3. table 13. rf memory access conditions at power-on access condition m24lrxx user memory sss byte read only sector 0 0000 1001b read and write sector 1 0000 1011b not accessible sector 2 0000 1101b not accessible sector 3 0000 1111b read and write ? 0000 0000b read and write sector 62 0000 0000b read and write sector 63 0000 0000b not accessible in rf i2c_write lock bit area not applicable write once in rf sector_securit y_status area not applicable
AN3002 m24lrxx?s conditional memory access doc id 15912 rev 2 17/22 m24lrxx memory access after a valid present-sector password command after a valid present-sector password command, the memory sector accesses are changed as shown in table 14: rf memory access condition after a valid present-sector password . the sector 0 can be updated by a write command, the sector 3 is now accessible in read mode, and the sector 2 is accessible in both read and write modes. this protection mechanism is submitted to an rf password value. the example above uses the password value 1 as defined by the sector security status bits b3 & b4. the m24lrxx provides 3 different passwords, so that 3 different applications can manage its memory access conditions. in the multiple rf password protection scheme, the m24lrxx memory can be divided into 6 different areas using the 4 different passwords conditions listed below: the public eeprom area, no password protection the public rom area, controlled by the password 0 condition the non-accessible area controlled by the password 0 condition the ?application 1? area protected by the password 1 the ?application 2? area protected by the password 2 the ?application 3? area protected by the password 3 it is not mandatory to have contiguous sectors affected to the same area as each individual sector in the m24lrxx can be set to any one of the 4 password conditions. table 14. rf memory access condition after a valid present-sector password access condition m24lrxx user memory sss byte read and write sector 0 0000 1001b read and write sector 1 0000 1011b read and write sector 2 0000 1101b read only sector 3 0000 1111b read and write ? 0000 0000b read and write sector 62 0000 0000b read and write sector 63 0000 0000b not accessible in rf i2c_write lock bit area not applicable write once in rf sector_secur ity_status area not applicable
m24lrxx?s conditional memory access AN3002 18/22 doc id 15912 rev 2 figure 6. rf multiple password memory access condition at power-up figure 7. rf multiple password memory access condition after password 1 presentation access condition m24lrxx user memory sectors password re a d only p ass word 2 not a cce ss i b le p ass word 3 not a cce ss i b le p ass word 1 re a d a nd write no p ass word not a cce ss i b le p ass word 2 re a d only p ub lic a re a rom p ass word 0 condition applic a tion a re a 2 applic a tion a re a 3 applic a tion a re a 1 p ub lic a re a eeprom applic a tion a re a 2 a i17126 not a cce ss i b le p ass word 0 condition non- a cce ss i b le a re a access condition m24lrxx user memory sectors password re a d only p ass word 2 not a cce ss i b le p ass word 3 read and write password 1 re a d a nd write no p ass word not a cce ss i b le p ass word 2 re a d only p ub lic a re a rom p ass word 0 condition applic a tion a re a 2 applic a tion a re a 3 application area 1 p ub lic a re a eeprom applic a tion a re a 2 a i17127 p ass word 0 condition not a cce ss i b le non- a cce ss i b le a re a
AN3002 m24lrxx?s conditional memory access doc id 15912 rev 2 19/22 figure 8. rf multiple password memory access condition after password 2 presentation using the password 0 condition the m24lrxx offers the po ssibility of permanently locking t he rf read/write access rights of a sector. the password 0 condition is applied by resetting (to ?0?) the bits b4 and b3 in the sector security status byte (see table 6: password control bits ), and then by issuing the rf lock-sector password command. the access rights defined by bits b2 and b1 (see ta bl e 5 : read / write protection bit setting ) are then applied in a permanent way. indeed, since the rf present-sector password command does not allow the use of password 0, the sector access rights once applied can no longer be modified. 4.1.3 mixed rf and i 2 c access mixed data access conditions between the main application (using the i 2 c bus) and the rf environment (using the rfid reader/writer) can be defined on the basis of the i 2 c and rf access conditions described in section 4.1.1: i2c access and section 4.1.2: rf access . the m24lrxx offers flexibility, allowing the shar ing of data or restricting their access as illustrated in figure 9: m24lrxx rf and i2c access condition mix . access condition m24lrxx user memory sectors password read and write password 2 not a cce ss i b le p ass word 3 not a cce ss i b le p ass word 1 re a d a nd write no p ass word read and write password 2 re a d only p ub lic a re a rom application area 2 applic a tion a re a 3 applic a tion a re a 1 p ub lic a re a eeprom application area 2 a i1712 8 p ass word 0 condition p ass word 0 condition not a cce ss i b le non- a cce ss i b le a re a
m24lrxx?s conditional memory access AN3002 20/22 doc id 15912 rev 2 figure 9. m24lrxx rf and i 2 c access condition mix 1. the lighter the shade the more rights, the darker the shade, the less rights (so that white indicates both read and write access rights whereas black means neither). it is simple to extend the rf capability of ex isting serial eeprom memory applications by using the scheme given in figure 10 . figure 10. example of an rf capability extension in an application running with an eeprom 1. the lighter the shade the more rights, the darker the shade, the less rights (so that white indicates both read and write access rights whereas black means neither). in figure 10 , the first part of the memory is limited to i 2 c access to ensure backward compatibility with the existing i 2 c serial access. the rest of the memory is shared between i 2 c and rf, making it possible to transfer data in both a ?contact? and a ?contactless? way, between the i 2 c interface application and the rfid reader. access rights for i 2 c m24lrxx user memory access rights for rf re a d a nd write s ector 0 s t a t us : s h a red re a d a nd write re a d a nd write s ector 1 s t a t us : i2c m as tered re a d only re a d a nd write s ector 2 s t a t us : i2c only not a cce ss i b le re a d only s ector 3 s t a t us : rf m as tered re a d a nd write re a d only s ector 4 s t a t us : re a d only re a d only re a d only s ector 5 s t a t us : i2c re a d only not a cce ss i b le ? re a d a nd write s ector 6 3 s t a t us : i2c only not a cce ss i b le 01010 01010 a i17129 access rights for i 2 c m24lrxx user memory access rights for rf re a d a nd write memory s ector s t a t us : i2c only not a cce ss i b le re a d a nd write memory s ector s t a t us : i2c only not a cce ss i b le re a d a nd write ? not a cce ss i b le re a d a nd write memory s ector s t a t us : i2c only not a cce ss i b le re a d a nd write memory s ector s t a t us : i2c only not a cce ss i b le re a d a nd write memory s ector s t a t us : s h a red re a d a nd write re a d a nd write memory s ector s t a t us : s h a red re a d a nd write re a d a nd write ? re a d a nd write re a d a nd write memory s ector s t a t us : s h a red re a d a nd write re a d a nd write memory s ector s t a t us : s h a red re a d a nd write 01010 01010 a i171 3 0
AN3002 revision history doc id 15912 rev 2 21/22 5 revision history table 15. document revision history date revision changes 26-jun-2009 1 initial release. 24-oct-2012 2 m24lr64-r replaced by m24lrxx-r and m24lrxxe-r on the cover page, then by m24lrxx (see note: ). added table 1: applicable products .
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